1. Field of the Invention
The present invention relates generally to the design and fabrication of packages for semiconductor devices. More particularly, it relates to a plastic semiconductor device package having an internal ground plane which provides for interlead isolation in order to reduce high frequency signal degradation within the package.
Individual semiconductor devices are usually packaged in either multilayer ceramic structures or placed on metal lead frames and encapsulated in plastic. Plastic packages are advantageous because of their low production costs and simplicity of manufacture. Ceramic packages, although substantially more expensive, are usually chosen in critical applications such as high temperature, high humidity, or the like. Of particular interest to the present invention, ceramic packages have generally been employed for high requency devices having operating frequencies in the megaHertz range and higher. In such high frequency applications, plastic packages have generally suffered from unacceptably high signal degradation.
Signal degradation can rise from a variety of factors, including variations in signal line impedance, capacitive and inductive coupling between adjacent signal lines, and the like. Impedance variations cause signal reflections and arise, in part, from lack of a suitable ground plane in most plastic semiconductor packages. Because of the methods of manufacture, i.e., mounting the semiconductor device on a lead frame and encapsulating the lead frame in the plastic material, it has been difficult to provide a second conductive layer within the package to act as a ground plane.
It would therefore be desirable to provide plastic semiconductor device packages having high frequency signal degradation characteristics approaching those of ceramic packages. In particular, it would be desirable to provide such plastic packages having an internal ground plane capable of minimizing variations in signal line resistance and capacitive loading between adjacent signal lines.
2. Description of the Background Art
U.S. Pat. No. 4,551,746 to Gilbert et al. discloses a ceramic semiconductor package having a metallized die attach pad connected to a metallization area by a via and a metallized castellation. U.S. Pat. No. 4,252,864 to Coldren describes a lead frame having leads which are intended to be folded over onto a device mounted on the frame. Schaper, (1981) Proc. First Annual Conference of the International Packaging Society Cleveland, Ohio, Nov. 9-10, pp. 38-42, describes inductance problems which can arise in packaging high frequency semiconductor devices; see, in particular, Section VIII. Copending application Ser. No. 557,119, assigned to the assignee of the present application, describes a low inductive impedance package having a semiconductor device mounted on a ground plane separate from a lead frame. The ground plane is connected to the device ground.